SH7606 Datasheet, PDF (335/532 Pages) Renesas Technology Corp – 32-Bit RISC Microcomputer SuperH™ RISC engine Family / SH7606 Series

Section 13 Host Interface (HIF)
Initial
Bit
Bit Name Value R/W Description
9
BMD
0
R/W HIFRAM Bank Mode
8
BSEL
0
R/W HIFRAM Bank Select
Controls the HIFRAM access mode.
00: Both an external device and the on-chip CPU can
access bank 0. When access by both of these
conflict, even though the access addresses differ,
access by the external device is processed before
access by the on-chip CPU. Bank 1 cannot be
accessed.
01: Both an external device and the on-chip CPU can
access bank 1. When access by both of these
conflict, even though the access addresses differ,
access by the external device is processed before
access by the on-chip CPU. Bank 0 cannot be
accessed.
10: An external device can access only bank 0 while
the on-chip CPU can access only bank 1.
11: An external device can access only bank 1 while
the on-chip CPU can access only bank 0.
7
—
0
R
Reserved
This bit is always read as 0. The write value should
always be 0.
6
—
1
R
Reserved
This bit is always read as 1. The write value should
always be 1.
Rev. 4.00 Sep. 13, 2007 Page 309 of 502
REJ09B0239-0400