SH7606 Datasheet, PDF (86/532 Pages) Renesas Technology Corp – 32-Bit RISC Microcomputer SuperH™ RISC engine Family / SH7606 Series

Section 3 Cache
Data-Array Write: Write the longword data specified by the data field, to the position specified
by L of the address field, in the entry that corresponds to the entry address and the way specified
by the address field.
(1) Address array access
(a) Address specification
Read access
31
1111 0000
24 23
Write access
31
1111 0000
24 23
*--------*
*--------*
14 13 12 11
43210
W Entry address 0 * 0 0
14 13 12 11
43210
W Entry address A * 0 0
(b) Data specification (both read and write accesses)
31 30 29 28
00 0
Tag address (28 to 10)
10 9
LRU
43210
X XU V
(2) Data array access (both read and write accesses)
(a) Address specification
31
24 23
1111 0001
*--------*
14 13 12 11
43210
W Entry address L 0 0
(b) Data specification
31
0
Longword
[Legend]
*: Don't care
X: 0 for read, don't care for write
Figure 3.4 Specifying Address and Data for Memory-Mapped Cache Access
Rev. 4.00 Sep. 13, 2007 Page 60 of 502
REJ09B0239-0400