SH7606 Datasheet, PDF (349/532 Pages) Renesas Technology Corp – 32-Bit RISC Microcomputer SuperH™ RISC engine Family / SH7606 Series

Section 13 Host Interface (HIF)
13.8 External DMAC Interface
Figures 13.8 to 13.11 show the HIFDREQ output timing. The start of the HIFDREQ assert
synchronizes with the DTRG bit in HIFDTR being set to 1. The HIFDREQ negate timing and
assert level are determined by the DMD and DPOL bits in HIFSCR, respectively.
When the external DMAC is specified to detect low level of the HIFDREQ signal, set DMD = 0
and DPOL = 0. After writing 1 to the DTRG bit, the HIFDREQ signal remains low until low level
is detected for both the HIFCS and HIFRS signals.
In this case, when the HIFDREQ signal is used, make sure that the setup time (HIFCS assertion to
HIFRS settling) and the hold time (HIFRS hold to HIFCS negate) are satisfied. If t_HIFAS and t_HIFAH
stipulated in section 19.4.9, HIF Timing, are not satisfied, the HIFDREQ signal may be negated
unintentionally.
DTRG bit
DPOL bit
HIFDREQ
HIFCS
HIFRS
Asserted in synchronization with the
DTRG bit being set by the on-chip CPU.
The DTRG bit is cleared
simultaneously with
HIFDREQ negate.
Negated when HIFCS = HIFRS = low level.
Latency is tPCYC (peripheral clock cycle) × 3 cyc or less.
Figure 13.8 HIFDREQ Timing (When DMD = 0 and DPOL = 0)
When the external DMAC is specified to detect high level of the HIFDREQ signal, set DMD = 0
and DPOL = 1. At the time the DPOL bit is set to 1, HIFDREQ becomes low. Then after writing 1
to the DTRG bit, HIFDREQ remains high until low level is detected for both the HIFCS and
HIFRS signals.
In this case, when the HIFDREQ signal is used, make sure that the setup time (HIFCS assertion to
HIFRS settling) and the hold time (HIFRS hold to HIFCS negate) are satisfied. If t_HIFAS and t_HIFAH
stipulated in section 19.4.9, HIF Timing, are not satisfied, the HIFDREQ signal may be negated
unintentionally.
Rev. 4.00 Sep. 13, 2007 Page 323 of 502
REJ09B0239-0400