SH7606 Datasheet, PDF (271/532 Pages) Renesas Technology Corp – 32-Bit RISC Microcomputer SuperH™ RISC engine Family / SH7606 Series

Section 12 Serial Communication Interface with FIFO (SCIF)
12.3.6 Serial Control Register (SCSCR)
SCSCR is a 16-bit register that operates the SCIF transmitter/receiver, enables/disables interrupt
requests, and selects the transmit/receive clock source. The CPU can always read and write to
SCSCR. SCSCR is initialized to H'0000 by a power-on reset.
Bit
15 to 8
Bit Name

7
TIE
Initial
value
All 0
0
R/W Description
R Reserved
These bits are always read as 0. The write value should
always be 0.
R/W Transmit Interrupt Enable
Enables or disables the transmit-FIFO-data-empty
interrupt (TXI).
Serial transmit data in the transmit FIFO data register
(SCFTDR) is send to the transmit shift register
(SCTSR). Then, the TDFE flag in the serial status
register (SCFSR) is set to1 when the number of data in
SCFTDR becomes less than the number of
transmission triggers. At this time, a TXI is requested.
0: Transmit-FIFO-data-empty interrupt request (TXI) is
disabled*
1: Transmit-FIFO-data-empty interrupt request (TXI) is
enabled
Note: * The TXI interrupt request can be cleared by
writing a greater number of transmit data than
the specified transmission trigger number to
SCFTDR and by clearing the TDFE bit to 0
after reading 1 from the TDFE bit, or can be
cleared by clearing this bit to 0.
Rev. 4.00 Sep. 13, 2007 Page 245 of 502
REJ09B0239-0400