SH7606 Datasheet, PDF (292/532 Pages) Renesas Technology Corp – 32-Bit RISC Microcomputer SuperH™ RISC engine Family / SH7606 Series

Section 12 Serial Communication Interface with FIFO (SCIF)
Initial
Bit
Bit Name value R/W Description
1
RFRST
0
R/W Receive FIFO Data Register Reset
Disables the receive data in the receive FIFO data
register and resets the data to the empty state.
0: Reset operation disabled*
1: Reset operation enabled
Note: * Reset operation is executed by a power-on
reset.
0
LOOP
0
R/W Loop-Back Test
Internally connects the transmit output pin (TxD) and
receive input pin (RxD) and enables loop-back testing.
0: Loop back test disabled
1: Loop back test enabled
Rev. 4.00 Sep. 13, 2007 Page 266 of 502
REJ09B0239-0400