SH7606 Datasheet, PDF (104/532 Pages) Renesas Technology Corp – 32-Bit RISC Microcomputer SuperH™ RISC engine Family / SH7606 Series

Section 5 Exception Handling
Types
Illegal slot instruction
General illegal instruction
Stack State
SP →
Address of
delayed branch instruction
SR
32 bits
32 bits
SP →
Address of
general illegal instruction
SR
32 bits
32 bits
Rev. 4.00 Sep. 13, 2007 Page 78 of 502
REJ09B0239-0400