SH7606 Datasheet, PDF (156/532 Pages) Renesas Technology Corp – 32-Bit RISC Microcomputer SuperH™ RISC engine Family / SH7606 Series

Section 7 Bus State Controller (BSC)
• CS6BWCR
Initial
Bit
Bit Name Value R/W
31 to 21 
All 0 R
20
BAS
0
R/W
19 to 13 
All 0 R
12
SW1
0
R/W
11
SW0
0
R/W
Description
Reserved
These bits are always read as 0. The write value should
always be 0.
Byte Access Selection for Byte-Selection SRAM
Specifies the WEn (BEn) and RD/WR signal timing when
the byte-selection SRAM interface is used.
0: Asserts the WEn (BEn) signal at the read/write timing
(signal used as strobe) and asserts the RD/WR signal
during the write access cycle (signal used as status)
1: Asserts the WEn (BEn) signal during the read/write
access cycle (used as status) and asserts the RD/WR
signal at the write timing (used as strobe)
Reserved
These bits are always read as 0. The write value should
always be 0.
Number of Delay Cycles from Address, CSn Assertion to
RD, WEn (BEn) Assertion
Specify the number of delay cycles from address and
CSn assertion to RD and WEn (BEn) assertion.
00: 0.5 cycles
01: 1.5 cycles
10: 2.5 cycles
11: 3.5 cycles
Rev. 4.00 Sep. 13, 2007 Page 130 of 502
REJ09B0239-0400