SH7606 Datasheet, PDF (48/532 Pages) Renesas Technology Corp – 32-Bit RISC Microcomputer SuperH™ RISC engine Family / SH7606 Series

Section 2 CPU
• Status register (SR)
Bit
31 to 10
9
8
7
6
5
4
3, 2
1
0
Bit
name

Default
All 0
M
Undefined
Q
Undefined
I3
1
I2
1
I1
1
I0
1

All 0
S
Undefined
T
Undefined
Read/
Write
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Description
Reserved
These bits are always read as 0. The write value
should always be 0.
Used by the DIV0U, DIV0S, and DIV1 instructions.
Used by the DIV0U, DIV0S, and DIV1 instructions.
Interrupt Mask
Reserved
These bits are always read as 0. The write value
should always be 0.
S
Used by the multiply and accumulate instruction.
T
Indicates true (1) or false (0) in the following
instructions: MOVT, CMP/cond, TAS, TST, BT (BT/S),
BF (BF/S), SETT, CLRT
Indicates carry, borrow, overflow, or underflow in the
following instructions: ADDV, ADDC, SUBV, SUBC,
NEGC, DIV0U, DIV0S, DIV1, SHAR, SHAL, SHLR,
SHLL, ROTR, ROTL, ROTCR, ROTCL
• Global-base register (GBR)
This register indicates a base address in GBR indirect addressing mode. The GBR indirect
addressing mode is used for data transfer of the on-chip peripheral module registers and logic
operations.
• Vector-base register (VBR)
This register indicates the base address of the exception handling vector table.
Rev. 4.00 Sep. 13, 2007 Page 22 of 502
REJ09B0239-0400