SH7606 Datasheet, PDF (423/532 Pages) Renesas Technology Corp – 32-Bit RISC Microcomputer SuperH™ RISC engine Family / SH7606 Series

Section 16 User Break Controller (UBC)
 Channel A
Address: H'00123456, Address mask: H'00000000, ASID = H'80
Bus cycle: L bus/data access/read (operand size is not included in the condition)
 Channel B
Address: H'000ABCDE, Address mask: H'000000FF
Data: H'0000A512, Data mask: H'00000000
Bus cycle: L bus/data access/write/word
On channel A, a user break occurs with longword read from address H'00123454, word read
from address H'00123456, or byte read from address H'00123456. On channel B, a user break
occurs when word H'A512 is written in addresses H'000ABC00 to H'000ABCFE.
Break Condition Specified for I Bus Data Access Cycle:
• Register specifications:
BARA = H'00314156, BAMRA = H'00000000, BBRA = H'0094, BARB = H'00055555,
BAMRB = H'00000000, BBRB = H'00A9, BDRB = H'00007878, BDMRB = H'00000F0F,
BRCR = H'00000080
Specified conditions: Channel A/channel B independent mode
 Channel A
Address: H'00314156, Address mask: H'00000000, ASID = H'80
Bus cycle: I bus/instruction fetch/read (operand size is not included in the condition)
 Channel B
Address: H'00055555, Address mask: H'00000000, ASID = H'70
Data: H'00000078, Data mask: H'0000000F
Bus cycle: I bus/data access/write/byte
On channel A, a user break occurs when instruction fetch is performed for address H'00314156
in the memory space.
On channel B, a user break occurs when the I bus writes byte data H'7* in address
H'00055555.
16.3.8 Usage Notes
1. The CPU can read from or write to the UBC registers via the I bus. Accordingly, during the
period from executing an instruction to rewrite the UBC register till the new value is actually
rewritten, the desired break may not occur. In order to know the timing when the UBC register
is changed, read from the last written register. Instructions after then are valid for the newly
written register value.
Rev. 4.00 Sep. 13, 2007 Page 397 of 502
REJ09B0239-0400