SH7606 Datasheet, PDF (138/532 Pages) Renesas Technology Corp – 32-Bit RISC Microcomputer SuperH™ RISC engine Family / SH7606 Series

Section 7 Bus State Controller (BSC)
Area P4 (H'E0000000 to H'EFFFFFFF) is an I/O area and is allocated to internal register
addresses. Therefore, area P4 does not become shadow space.
H'00000000
H'20000000
P0
H'40000000
H'60000000
H'80000000
P1
H'A0000000
P2
H'C0000000
P3
H'E0000000
P4
Area 0 (CS0)
Area 1 (reserved)
Area 2 (reserved)
Area 3 (CS3)
Area 4 (CS4)
Area 5A (reserved)
Area 5B (CS5B)
Area 6A (reserved)
Area 6B (CS6B)
Area 7 (reserved)
Physical address space
Address Space
Figure 7.2 Address Space
7.3.3 Address Map
The external address space has a capacity of 256 Mbytes and is divided into five areas. Types of
memory to be connected and the data bus width are specified for individual areas. The address
map for the external address space is shown in table 7.2.
Table 7.2 Address Map 1 (CMNCR.MAP = 0)
Physical Address
H'00000000 to H'03FFFFFF
H'04000000 to H'07FFFFFF
H'08000000 to H'0BFFFFFF
H'0C000000 to H'0FFFFFFF
Area
Area 0
Area 1
Area 2
Area 3
Memory to be Connected
Normal memory
Reserved area*
Reserved area*
Normal memory
Byte-selection SRAM
SDRAM
Capacity
64 Mbytes
64 Mbytes
64 Mbytes
64 Mbytes
Rev. 4.00 Sep. 13, 2007 Page 112 of 502
REJ09B0239-0400