SH7606 Datasheet, PDF (93/532 Pages) Renesas Technology Corp – 32-Bit RISC Microcomputer SuperH™ RISC engine Family / SH7606 Series

Section 5 Exception Handling
5.1.3 Exception Handling Vector Table
Before exception handling starts, the exception handling vector table must be set in memory. The
exception handling vector table stores the start addresses of exception handling routines. (The
reset exception handling table holds the initial values of PC and SP.)
All exception sources are given different vector numbers and vector table address offsets. The
vector table addresses are calculated from these vector numbers and vector table address offsets.
During exception handling, the start addresses of the exception handling routines are fetched from
the exception handling vector table that is indicated by this vector table address.
Table 5.3 shows the vector numbers and vector table address offsets. Table 5.4 shows how vector
table addresses are calculated.
Table 5.3 Vector Numbers and Vector Table Address Offsets
Exception Handling Source
Power-on reset
PC
H-UDI reset
SP
(Reserved by
system)
General illegal instruction
(Reserved by system)
Illegal slot instruction
(Reserved by system)
CPU address error
(Reserved by system)
Interrupt
NMI
User break
H-UDI
(Reserved by system)
Vector Number
0
1
2
3
4
5
6
7
8
9
10
11
12
13
14
:
31
Vector Table Address Offset
H'00000000 to H'00000003
H'00000004 to H'00000007
H'00000008 to H'0000000B
H'0000000C to H'0000000F
H'00000010 to H'00000013
H'00000014 to H'00000017
H'00000018 to H'0000001B
H'0000001C to H'0000001F
H'00000020 to H'00000023
H'00000024 to H'00000027
H'00000028 to H'0000002B
H'0000002C to H'0000002F
H'00000030 to H'00000033
H'00000034 to H'00000037
H'00000038 to H'0000003B
:
H'0000007C to H'0000007F
Rev. 4.00 Sep. 13, 2007 Page 67 of 502
REJ09B0239-0400