SH7606 Datasheet, PDF (227/532 Pages) Renesas Technology Corp – 32-Bit RISC Microcomputer SuperH™ RISC engine Family / SH7606 Series

Section 8 Clock Pulse Generator (CPG)
Notes: 1. When the MDCHG bit in STBCR is set to 1, changing the FRQCR value has no effect
on the operation immediately. For details, see section 8.5.3, Changing Clock Operating
Mode.
2. The multiplication ratio should be changed after completion of the operation, if the on-
chip peripheral module is operating. The internal and peripheral clocks are stopped
during the multiplication ratio is changed. The communication error may occur by the
peripheral module communicating to the external IC, and the time error may occur by
the timer unit (except the WDT). The edge detection of external interrupts (NMI and
IRQ7 to IRQ0) cannot be performed.
8.5.2 Changing Division Ratio
The WDT will not count unless the multiplication ratio is changed simultaneously.
1. In the initial state, PFC2 to PFC0 = 011.
2. Set the desired values in bits PFC2 to PFC0 while the MDCHG bit in STBCR is 0. The values
that can be set are limited by the clock mode and the multiplication ratio of PLL circuit 1. Note
that if the wrong value is set, this LSI will malfunction.
3. The clock is immediately changed to the new division ratio.
Note: When the MDCHG bit in STBCR is set to 1, changing the FRQCR value has no effect on
the operation immediately. For details, see section 8.5.3, Changing Clock Operating
Mode.
Rev. 4.00 Sep. 13, 2007 Page 201 of 502
REJ09B0239-0400