SH7606 Datasheet, PDF (334/532 Pages) Renesas Technology Corp – 32-Bit RISC Microcomputer SuperH™ RISC engine Family / SH7606 Series

Section 13 Host Interface (HIF)
Initial
Bit
Bit Name Value R/W Description
11
DMD
0
R/W DREQ Mode
10
DPOL
0
R/W DREQ Polarity
Controls the assert mode for the HIFDREQ pin. For
details on the negate timing, see section 13.8,
External DMAC Interface.
00: For a DMAC transfer request to an external
device, low level is generated at the HIFDREQ
pin. The default for the HIFDREQ pin is high-level
output.
01: For a DMAC transfer request to an external
device, high level is generated at the HIFDREQ
pin. The default for the HIFDREQ pin is low-level
output.
10: For a DMAC transfer request to an external
device, falling edge is generated at the HIFDREQ
pin. The default for the HIFDREQ pin is high-level
output.
11: For a DMAC transfer request to an external
device, rising edge is generated at the HIFDREQ
pin. The default for the HIFDREQ pin is low-level
output.
Rev. 4.00 Sep. 13, 2007 Page 308 of 502
REJ09B0239-0400