SH7606 Datasheet, PDF (519/532 Pages) Renesas Technology Corp – 32-Bit RISC Microcomputer SuperH™ RISC engine Family / SH7606 Series

Main Revisions and Additions in this Edition
Item
12.3.7 Serial Status Register (SCFSR)
12.4.3 Synchronous Mode
Page Revision (See Manual for Details)
252 Amended.
Bit Description
5 [Clearing conditions]
• TDFE is cleared to 0 when data exceeding the
specified transmission trigger number is written to
SCFTDR after 1 is read from the TDFE bit and then 0
is written
• TDFE is cleared to 0 when DMAC write data
exceeding the specified transmission trigger number
to SCFTDR
1: The number of transmit data in SCFTDR is equal to or
less than the specified transmission trigger number*
[Setting conditions]
• TDFE is set to 1 by a power-on reset
• TDFE is set to 1 when the number of transmit data in
SCFTDR becomes equal to or less than the specified
transmission trigger number as a result of
transmission
Note: *Since SCFTDR is a 16-byte FIFO register, the
maximum number of data that can be written when TDFE
is 1 is "16 minus the specified transmission trigger
number". If an attempt is made to write additional data, the
data is ignored. The number of data in SCFTDR is
indicated by the upper 8 bits of SCFDR.
287 Added.
……When the SCIF is not transmitting or receiving, the clock signal
remains in the high state. When only receiving, the clock signal outputs
while the RE bit of SCSCR is 1 and the number of data in receive FIFO
is less than the receive FIFO data trigger number. In this case, 8 × (16
+ 1) = 136 pulses of synchronous clock are output. To perform
reception of n characters of data, select an external clock as the clock
source. If an internal clock should be used, set RE = 1 and TE = 1 and
receive n characters of data simultaneously with the transmission of n
characters of dummy data.
Rev. 4.00 Sep. 13, 2007 Page 493 of 502
REJ09B0239-0400