SH7606 Datasheet, PDF (326/532 Pages) Renesas Technology Corp – 32-Bit RISC Microcomputer SuperH™ RISC engine Family / SH7606 Series

Section 12 Serial Communication Interface with FIFO (SCIF)
The receive margin in asynchronous mode can therefore be expressed as shown in equation 1.
Equation 1:
M = (0.5 - ¹ ) = (L - 0.5) F - ^{D - 0.5} (1+F) × 100 %
2N
N
Where: M: Receive margin (%)
N: Ratio of clock frequency to bit rate (N = 16)
D: Clock duty cycle (D = 0 to 1.0)
L: Frame length (L = 9 to 12)
F: Absolute deviation of clock frequency
From equation 1, if F = 0 and D = 0.5, the receive margin is 46.875%, as given by equation 2.
Equation 2:
When D = 0.5 and F = 0:
M
= (0.5 – 1/(2 × 16)) × 100%
= 46.875%
This is a theoretical value. A reasonable margin to allow in system designs is 20% to 30%.
6. Prohibited Multiple Pin Allocation for Channel 1
Although signal SCK1, RxD1, or TxD1 can be assigned to pin PD4 or PE20, either of the pin
must be selected. For example, if signal SCK1 is assigned to both pins PD4 and PE20, correct
operation of the SCIF is not guaranteed. Similarly, signal SCK1, RxD1, or TxD1 can be
assigned to pin PD3 or PE19 and pin PD2 or PE18, respectively. However if these signals are
assigned to both corresponding pins, correct operation of the SCIF is not guaranteed.
7. States of the TxD and RTS Pins When the TE Bit is Cleared
The TxDi (i = 0, 1, 2) and RTSj (j = 0, 1) pins usually function as output pins during serial
communication. However, even if these functions are selected by the pin function controller
(PFC), these pins are in the high impedance state as long as the TE bit in SCSCRi (i = 0, 1, 2)
is cleared. To make these pins always function as output pins (regardless of the value of the TE
bit), set SCPTRi (i = 0, 1, 2) and PFC in the following order.
a. Set the SPBIO and SPBDT bits in SCPTRi (i = 0, 1, 2). Set the RTSIO and RTSDT bits in
SCPTRj (j = 0, 1).
b. Select the TxDi (i = 0, 1, 2) and RTSj (j = 0, 1) pins by the PFC.
8. Interval from when the TE bit in SCSCR is Set to 1 until a Start Bit is Transmitted in
Asynchronous Mode
In the SCIF included in former products, a start bit is transmitted after the internal equivalent
to one frame. In the SCIF included in this product, however, a start bit is transmitted directly
after the TE bit is set to 1.
Rev. 4.00 Sep. 13, 2007 Page 300 of 502
REJ09B0239-0400