SH7606 Datasheet, PDF (232/532 Pages) Renesas Technology Corp – 32-Bit RISC Microcomputer SuperH™ RISC engine Family / SH7606 Series

Section 9 Watchdog Timer (WDT)
Standby
cancellation
Internal
reset
request
Interrupt
request
Standby
control
WDT
Reset
control
Interrupt
control
Clock selection
Overflow
Divider
Clock selector
Clock
WTCSR
WTCNT
Bus interface
Standby
mode
Peripheral
clock (Pφ)
[Legend]
WTCSR:
WTCNT:
Watchdog timer control/status register
Watchdog timer counter
Figure 9.1 Block Diagram of WDT
9.2 Register Descriptions
The WDT has the following two registers. For details on the addresses of these registers and the
states of these registers in each processing state, see section 18, List of Registers.
• Watchdog timer counter (WTCNT)
• Watchdog timer control/status register (WTCSR)
9.2.1 Watchdog Timer Counter (WTCNT)
WTCNT is an 8-bit readable/writable register that increments on the selected clock. When an
overflow occurs, it generates a reset in watchdog timer mode and an interrupt in interval time
mode. WTCNT is not initialized by an internal power-on reset due to the WDT overflow. WTCNT
is initialized to H'00 by a power-on reset input to the pin and an H-UDI reset.
Use a word access to write to WTCNT, with H'5A in the upper byte. Use a byte access to read
WTCNT.
Rev. 4.00 Sep. 13, 2007 Page 206 of 502
REJ09B0239-0400