SH7606 Datasheet, PDF (291/532 Pages) Renesas Technology Corp – 32-Bit RISC Microcomputer SuperH™ RISC engine Family / SH7606 Series

Section 12 Serial Communication Interface with FIFO (SCIF)
Initial
Bit
Bit Name value R/W Description
5
TTRG1
0
R/W Transmit FIFO Data Trigger 1 and 0
4
TTRG0
0
R/W Set the specified transmit trigger number. The transmit
FIFO data register empty (TDFE) flag in the serial
status register (SCFSR) is set when the number of
transmit data in the transmit FIFO data register
(SCFTDR) becomes less than the specified trigger
number shown below.
00: 8 (8)*
01: 4 (12)*
10: 2 (14)*
11: 0 (16)*
Note: * Values in parentheses mean the number of
remaining bytes in SCFTDR when the TDFE
flag is set to 1.
3
MCE
0
R/W Modem Control Enable
Enables modem control signals CTS and RTS.
In synchronous mode, clear this bit to 0.
This bit is available only in SCFCR_0 and SCFCR_1. In
SCFCR_2, this bit is reserved. The initial value is 0 and
the write value should always be 0.
0: Modem signal disabled*
1: Modem signal enabled
Note: * The CTS signal is fixed active 0 regardless of
the input value, and the RTS signal is also
fixed 0.
2
TFRST
0
R/W Transmit FIFO Data Register Reset
Disables the transmit data in the transmit FIFO data
register and resets the data to the empty state.
0: Reset operation disabled*
1: Reset operation enabled
Note: * Reset operation is executed by a power-on
reset.
Rev. 4.00 Sep. 13, 2007 Page 265 of 502
REJ09B0239-0400