SH7606 Datasheet, PDF (25/532 Pages) Renesas Technology Corp – 32-Bit RISC Microcomputer SuperH™ RISC engine Family / SH7606 Series

Section 13 Host Interface (HIF)
Table 13.1 Pin Configuration.................................................................................................. 303
Table 13.2 HIF Operations ..................................................................................................... 304
Table 13.3 Memory Map ........................................................................................................ 319
Table 13.4 Consecutive Write Procedure to HIFRAM by External DMAC........................... 326
Table 13.5 Consecutive Read Procedure from HIFRAM by External DMAC....................... 327
Table 13.6 Input/Output Control for HIF Pins........................................................................ 330
Section 14 Pin Function Controller (PFC)
Table 14.1 List of Multiplexed Pins (Port A) ......................................................................... 333
Table 14.2 List of Multiplexed Pins (Port B).......................................................................... 334
Table 14.3 List of Multiplexed Pins (Port C).......................................................................... 336
Table 14.4 List of Multiplexed Pins (Port D) ......................................................................... 336
Table 14.5 List of Multiplexed Pins (Port E).......................................................................... 337
Table 14.6 Pin Functions in Each Operating Mode ................................................................ 338
Section 15 I/O Ports
Table 15.1 Port A Data Register H (PADRH) Read/Write Operation .................................... 364
Table 15.2 Port B Data Register L (PBDRL) Read/Write Operation ..................................... 366
Table 15.3 Port C Data Registers H and L (PCDRH and PCDRL) Read/Write Operation .... 369
Table 15.4 Port D Data Register L (PDDRL) Read/Write Operation..................................... 371
Table 15.5 Port E Data Registers H, L (PEDRH, PEDRL) Read/Write Operation ................ 374
Section 16 User Break Controller (UBC)
Table 16.1 Data Access Cycle Addresses and Operand Size Comparison Conditions ........... 391
Section 17 User Debugging Interface (H-UDI)
Table 17.1 Pin Configuration.................................................................................................. 401
Table 17.2 H-UDI Commands................................................................................................ 403
Table 17.3 External Pins and Boundary Scan Register Bits ................................................... 404
Table 17.4 Reset Configuration .............................................................................................. 411
Section 19 Electrical Characteristics
Table 19.1 Absolute Maximum Ratings ................................................................................. 439
Table 19.2 Recommended Timing at Power-On..................................................................... 440
Table 19.3 Recommended Timing in Power-Off.................................................................... 441
Table 19.4 DC Characteristics (1)........................................................................................... 442
Table 19.4 DC Characteristics (2)........................................................................................... 443
Table 19.5 Permissible Output Currents ................................................................................. 444
Table 19.6 Maximum Operating Frequency ........................................................................... 444
Table 19.7 Clock Timing ........................................................................................................ 445
Table 19.8 Control Signal Timing .......................................................................................... 448
Table 19.9 Bus Timing ........................................................................................................... 450
Rev. 4.00 Sep. 13, 2007 Page xxv of xxvi