SH7606 Datasheet, PDF (505/532 Pages) Renesas Technology Corp – 32-Bit RISC Microcomputer SuperH™ RISC engine Family / SH7606 Series

Section 19 Electrical Characteristics
19.4.7 SCIF Timing
Table 19.10 SCIF Timing
Conditions: V_CCQ = 3.0 V to 3.6 V, V_CC = 1.4 V to 1.6 V,
T_a = –20°C to +75°C (regular specifications),
T_a = –40°C to +85°C (wide-range specifications)
Item
Symbol Min. Max.
Unit
Input clock cycle Clocked
t_Scyc
12 
t_pcyc
synchronous
Asynchronous t
Scyc
Input clock rising time
t
SCKR
Input clock falling time
t
SCKF
Input clock pulse width
t_SCKW
Transmit data delay time
t
TXD
Receive data setup time (clocked t_RXS
synchronous)
4
t
pcyc
 0.8
t
pcyc
 0.8
t
pcyc
0.4 0.6
t_Scyc
 3 × t_pcyc*+ 50 ns
3
t_pcyc
Receive data hold time (clocked t_RXH
3
t_pcyc
synchronous)
RTS delay time
CTS setup time (clocked
synchronous)
t
RTSD
 100
ns
t
CTSS
100 
ns
CTS hold time (clocked
synchronous)
t_CTSH
100 
ns
Note: * t_pcyc indicates the period of the peripheral clock (Pφ).
Reference Figures
Figures 19.37 and
19.38
Figure 19.37
Figure 19.38
SCK
t_SCKW
t_SCKR
t_Scyc
t_SCKF
Figure 19.37 SCK Input Clock Timing
Rev. 4.00 Sep. 13, 2007 Page 479 of 502
REJ09B0239-0400