SH7606 Datasheet, PDF (151/532 Pages) Renesas Technology Corp – 32-Bit RISC Microcomputer SuperH™ RISC engine Family / SH7606 Series

Section 7 Bus State Controller (BSC)
Bit
6
5 to 0
Initial
Bit Name Value R/W
WM
0
R/W

All 0 R
Description
External Wait Mask Specification
Specify whether or not the external wait input is valid.
The specification by this bit is valid even when the
number of access wait cycle is 0.
0: External wait is valid
1: External wait is ignored
Reserved
These bits are always read as 0. The write value should
always be 0.
• CS4WCR
Initial
Bit
Bit Name Value R/W
31 to 21 
All 0 R
20
BAS
0
R/W
19

0
R
Description
Reserved
These bits are always read as 0. The write value should
always be 0.
Byte Access Selection for Byte-Selection SRAM
Specifies the WEn (BEn) and RD/WR signal timing when
the byte-selection SRAM interface is used.
0: Asserts the WEn (BEn) signal at the read/write timing
(signal used as strobe) and asserts the RD/WR signal
during the write access cycle (signal used as status)
1: Asserts the WEn (BEn) signal during the read/write
access cycle (signal used as status) and asserts the
RD/WR signal at the write timing (signal used as
strobe)
Reserved
This bit is always read as 0. The write value should
always be 0.
Rev. 4.00 Sep. 13, 2007 Page 125 of 502
REJ09B0239-0400