SH7606 Datasheet, PDF (258/532 Pages) Renesas Technology Corp – 32-Bit RISC Microcomputer SuperH™ RISC engine Family / SH7606 Series

Section 11 Compare Match Timer (CMT)
Peripheral operating
clock (Pφ)
Address
CMCSR write cycle
T1
T2
CMCNT
Internal write
CMCNT count-up
enable
CMCNT
N
M
Figure 11.6 Conflict between Word-Write and Count-Up Processes of CMCNT
11.5.3 Conflict between Byte-Write and Count-Up Processes of CMCNT
Even when the count-up occurs in the T2 cycle while writing to CMCNT in bytes, the byte-writing
has priority over the count-up. In this case, the count-up is not performed. The byte data on
another side, which is not written to, is also not counted and the previous contents remain.
Figure 11.7 shows the timing when the count-up occurs in the T2 cycle while writing to CMCNT
in bytes.
Rev. 4.00 Sep. 13, 2007 Page 232 of 502
REJ09B0239-0400