SH7606 Datasheet, PDF (210/532 Pages) Renesas Technology Corp – 32-Bit RISC Microcomputer SuperH™ RISC engine Family / SH7606 Series

Section 7 Bus State Controller (BSC)
This LSI
A16
A1
CSn
RD
RD/WR
D15
D0
WE1(BE1)
WE0(BE0)
64 kwords x 16 bits
SRAM
A16
A1
CS
OE
WE
I/O 15
I/O 0
UB
LB
Figure 7.29 Example of Connection with 16-Bit Data-Width Byte-Selection SRAM
7.5.7 PCMCIA Interface
With this LSI, if address map 2 is selected using the MAP bit in CMNCR, the PCMCIA interface
can be specified in areas 5 and 6. Areas 5 and 6 in the physical space can be used for the IC
memory card and I/O card interface defined in the JEIDA specifications version 4.2 (PCMCIA2.1
Rev. 2.1) by specifying bits TYPE3 to TYPE0 in CSnBCR (n = 5B and 6B) to B'0101. In addition,
bits SA1 and SA0 in CSnWCR (n = 5B and 6B) assign the upper or lower 32 Mbytes of each area
to an IC memory card or I/O card interface. For example, if bits SA1 and SA0 in CS5BWCR are
set to 1 and cleared to 0, respectively, the upper 32 Mbytes and the lower 32 Mbytes of area 5B
are used as an IC memory card interface and I/O card interface, respectively.
When the PCMCIA interface is used, the bus size must be specified as 8 bits or 16 bits using bits
BSZ1 and BSZ0 in CS5BBCR or CS6BBCR.
Figure 7.30 shows an example of a connection between this LSI and the PCMCIA card. To enable
insertion and removal of the PCMCIA card with the system power turned on, tri-state buffers must
be connected between the LSI and the PCMCIA card.
In the JEIDA and PCMCIA standards, operation in big endian mode is not clearly defined.
Consequently, the provided PCMCIA interface in big endian mode is available only for this LSI.
Rev. 4.00 Sep. 13, 2007 Page 184 of 502
REJ09B0239-0400