SH7606 Datasheet, PDF (163/532 Pages) Renesas Technology Corp – 32-Bit RISC Microcomputer SuperH™ RISC engine Family / SH7606 Series

Section 7 Bus State Controller (BSC)
Initial
Bit
Bit Name Value R/W Description
6
WM
0
R/W External Wait Mask Specification
Specify whether or not the external wait input is valid.
The specification by this bit is valid even when the
number of access wait cycle is 0.
0: External wait is valid
1: External wait is ignored
5, 4

All 0 R
Reserved
These bits are always read as 0. The write value should
always be 0.
3
TEH3
0
R/W Delay from RD or WE Negate to Address
2
TEH2
0
R/W Specify the address hold time from RD or WE negation in
1
TEH1
0
R/W ^{the PCMCIA interface.}
0
TEH0
0
R/W ^{0000: 0.5 cycle}
0001: 1.5 cycles
0010: 2.5 cycles
0011: 3.5 cycles
0100: 4.5 cycles
0101: 5.5 cycles
0110: 6.5 cycles
0111: 7.5 cycles
1000: 8.5 cycles
1001: 9.5 cycles
1010: 10.5 cycles
1011: 11.5 cycles
1100: 12.5 cycles
1101: 13.5 cycles
1110: 14.5 cycles
1111: 15.5 cycles
Rev. 4.00 Sep. 13, 2007 Page 137 of 502
REJ09B0239-0400