SH7606 Datasheet, PDF (290/532 Pages) Renesas Technology Corp – 32-Bit RISC Microcomputer SuperH™ RISC engine Family / SH7606 Series

Section 12 Serial Communication Interface with FIFO (SCIF)
Bit
Bit Name
15 to 11 
10
RSTRG2
9
RSTRG1
8
RSTRG0
7
RTRG1
6
RTRG0
Initial
value
All 0
0
0
0
0
0
R/W Description
R Reserved
These bits are always read as 0. The write value should
always be 0.
R/W RTS Output Active Trigger
R/W When the number of receive data in the receive FIFO
R/W
register (SCFRDR) becomes more than the number
shown below, the RTS signal is set to high.
These bits are available only in SCFCR_0 and
SCFCR_1. In SCFCR_2, these bits are reserved. The
initial value is 0 and the write value should always be 0.
000: 15
001: 1
010: 4
011: 6
100: 8
101: 10
110: 12
111: 14
R/W Receive FIFO Data Trigger
R/W Set the specified receive trigger number. The receive
data full (RDF) flag in the serial status register (SCFSR)
is set when the number of receive data stored in the
receive FIFO register (SCFRDR) exceeds the specified
trigger number shown below.
• Asynchronous mode
00: 1
01: 4
10: 8
11: 14
• Synchronous mode
00: 1
01: 2
10: 8
11: 14
Rev. 4.00 Sep. 13, 2007 Page 264 of 502
REJ09B0239-0400