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SH7606 Datasheet, PDF (73/532 Pages) Renesas Technology Corp – 32-Bit RISC Microcomputer SuperH™ RISC engine Family / SH7606 Series | |||
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Section 2 CPU
Instruction
Operation
Code
Execution
Cycles
T Bit
STS MACL,Rn
MACL â Rn
0000nnnn00011010 1

STS PR,Rn
PR â Rn
0000nnnn00101010 1

STS.L MACH,@âRn
Rnâ4 â Rn, MACH â (Rn) 0100nnnn00000010 1

STS.L MACL,@âRn
Rnâ4 â Rn, MACL â (Rn) 0100nnnn00010010 1

STS.L PR,@âRn
Rnâ4 â Rn, PR â (Rn) 0100nnnn00100010 1

TRAPA #imm
PC/SR â Stack area,
11000011iiiiiiii 8

(imm à 4 + VBR) â PC
Note: * Number of execution cycles until this LSI enters sleep mode.
About the number of execution cycles:
The table lists the minimum number of execution cycles. In practice, the number of
execution cycles will be increased depending on the conditions such as:
⢠When there is a conflict between instruction fetch and data access
⢠When the destination register of a load instruction (memory â register) is also used
by the instruction immediately after the load instruction.
Rev. 4.00 Sep. 13, 2007 Page 47 of 502
REJ09B0239-0400
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