SH7606 Datasheet, PDF (194/532 Pages) Renesas Technology Corp – 32-Bit RISC Microcomputer SuperH™ RISC engine Family / SH7606 Series

Section 7 Bus State Controller (BSC)
Single Write: A write access ends in one cycle when data is written in non-cacheable area and the
data bus width is larger than or equal to access size.
Figure 7.16 shows the single write basic timing.
CKIO
A25 to A0
A11*
CSn
RAS
CAS
RD/WR
DQMxx
D15 to D0
BS
Tr
Tc1 Trwl
Tap
Note: * Address pin to be connected to pin A10 of SDRAM.
Figure 7.16 Basic Timing for Single Write (Auto-Precharge)
Bank Active: The synchronous DRAM bank function is used to support high-speed accesses to
the same row address. When the BACTV bit in SDCR is 1, accesses are performed using
commands without auto-precharge (READ or WRIT). This function is called bank-active function.
When a bank-active function is used, precharging is not performed when the access ends. When
accessing the same row address in the same bank, it is possible to issue the READ or WRIT
command immediately, without issuing an ACTV command. Since synchronous DRAM is
internally divided into several banks, it is possible to keep one row address in each bank activated.
If the next access is to a different row address, a PRE command is first issued to precharge the
relevant bank, then when precharging is completed, the access is performed by issuing an ACTV
command followed by a READ or WRIT command. If this is followed by an access to a different
row address, the access time will be longer because of the precharging performed after the access
request is issued. The number of cycles between issuance of the PRE command and the ACTV
command is determined by bits WTRP1 and WTRP0 in CSnWCR.
Rev. 4.00 Sep. 13, 2007 Page 168 of 502
REJ09B0239-0400