SH7606 Datasheet, PDF (257/532 Pages) Renesas Technology Corp – 32-Bit RISC Microcomputer SuperH™ RISC engine Family / SH7606 Series

11.5 Usage Notes
Section 11 Compare Match Timer (CMT)
11.5.1 Conflict between Write and Compare-Match Processes of CMCNT
When the compare match signal is generated in the T2 cycle while writing to CMCNT, clearing
CMCNT has priority over writing to it. In this case, CMCNT is not written to. Figure 11.5 shows
the timing to clear the CMCNT counter.
Peripheral operating
clock (Pφ)
CMCSR write cycle
T1
T2
Address
CMCNT
Internal write
Counter clear
CMCNT
N
H'0000
Figure 11.5 Conflict between Write and Compare-Match Processes of CMCNT
11.5.2 Conflict between Word-Write and Count-Up Processes of CMCNT
Even when the count-up occurs in the T2 cycle while writing to CMCNT in words, the writing has
priority over the count-up. In this case, the count-up is not performed. Figure 11.6 shows the
timing to write to CMCNT in words.
Rev. 4.00 Sep. 13, 2007 Page 231 of 502
REJ09B0239-0400