SH7606 Datasheet, PDF (338/532 Pages) Renesas Technology Corp – 32-Bit RISC Microcomputer SuperH™ RISC engine Family / SH7606 Series

Section 13 Host Interface (HIF)
Initial
Bit
Bit Name Value R/W Description
2, 1 —
All 0
R
Reserved
These bits are always read as 0. The write value should
always be 0.
0
AI/AD
0
R/W* Address Auto-Increment/Decrement
This bit is valid only when the LOCK bit is 1. The value of
HIFADR is automatically incremented by 4 or
decremented by 4 according to the setting of this bit each
time reading or writing of HIFRAM is performed.
0: Auto-increment mode (+4)
1: Auto-decrement mode (−4)
Note: * This bit can be only written to by an external device when the HIFRS pin is low. It
cannot be written to by the on-chip CPU. Changing the HIFRAM banks accessible from
an external device by setting the BMD and BSEL bits in HIFSCR does not affect the
setting of this bit.
13.4.5 HIF Internal Interrupt Control Register (HIFIICR)
HIFIICR is a 32-bit register used to issue interrupts from an external device connected to the HIF
to the on-chip CPU. Access to HIFIICR by an external device should be performed with HIFIICR
specified by bits REG5 to REG0 in HIFIDX and the HIFRS pin low.
Rev. 4.00 Sep. 13, 2007 Page 312 of 502
REJ09B0239-0400