SH7606 Datasheet, PDF (46/532 Pages) Renesas Technology Corp – 32-Bit RISC Microcomputer SuperH™ RISC engine Family / SH7606 Series

Section 2 CPU
General register (Rn)
31
0
R0*¹
R1
R2
R3
R4
R5
R6
R7
R8
R9
R10
R11
R12
R13
R14
R15, SP (hardware stack pointer)0*²
Status register (SR)
31
9 87 6 5 4 3 210
M Q I3 I2 I1 I0
ST
Global base register (GBR)
31
0
GBR
Vector base register (VBR)
31
0
VBR
Multiply and accumulate register (MAC)
31
0
MACH
MACL
Procedure register (PR)
31
0
PR
Program counter (PC)
31
0
PC
Notes: 1. R0 can be used as an index register in index register indirect or index GBR
indirect addressing mode. For some instructions, only R0 is used as the
source or destination register.
2. R15 is used as a hardware stack pointer during exception handling.
Figure 2.1 CPU Internal Register Configuration
Rev. 4.00 Sep. 13, 2007 Page 20 of 502
REJ09B0239-0400