SH7606 Datasheet, PDF(277/532 Page) Renesas Technology Corp – 32-Bit RISC Microcomputer SuperH™ RISC engine Family / SH7606 Series

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SH7606 Datasheet, PDF (277/532 Pages) Renesas Technology Corp – 32-Bit RISC Microcomputer SuperH™ RISC engine Family / SH7606 Series

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Section 12 Serial Communication Interface with FIFO (SCIF)

Initial

Bit

Bit Name value R/W Description

6

TEND

1

R/(W)* Transmit End

Indicates that when the last bit of a serial character

was transmitted, SCFTDR did not contain valid data,

so transmission has ended.

0: Transmission is in progress

[Clearing condition]

TEND is cleared to 0 when 0 is written after 1 is read

from TEND after transmit data is written in SCFTDR

1: End of transmission

[Setting conditions]

â¢ TEND is set to 1 when the chip is a power-on

reset

â¢ TEND is set to 1 when TE is cleared to 0 in the

serial control register (SCSCR)

â¢ TEND is set to 1 when SCFTDR does not contain

receive data when the last bit of a one-byte serial

character is transmitted

Rev. 4.00 Sep. 13, 2007 Page 251 of 502

REJ09B0239-0400

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