SH7606 Datasheet, PDF (56/532 Pages) Renesas Technology Corp – 32-Bit RISC Microcomputer SuperH™ RISC engine Family / SH7606 Series

Section 2 CPU
Addressing
Mode
Index GBR
indirect
Instruction
Format Effective Address Calculation Method
@(R0,
GBR)
Effective address is sum of register GBR and
R0 contents.
GBR
Calculation
Formula
GBR + R0
PC relative with @(disp:8,
displacement PC)
+
GBR + R0
R0
Effective address is PC with 8-bit displacement Word: PC + disp
disp added. After disp is zero-extended, it is
×2
multiplied by 2 (word) or 4 (longword), according _Longword:
to the operand size. With a longword operand, _{PC&H'FFFFFFFC}
the lower 2 bits of PC are masked.
+ disp × 4
PC
*With longword operand
&^*
H'FFFFFFFC
+
disp (zero-extended)
×
PC + disp × 2
or
PC&
H'FFFFFFFC
+ disp × 4
PC relative
disp:8
2/4
Effective address is PC with 8-bit displacement
disp added after being sign-extended and
multiplied by 2.
PC + disp × 2
PC
disp
(sign-extended)
+
PC + disp × 2
×
disp:12
2
Effective address is PC with 12-bit displacement PC + disp × 2
disp added after being sign-extended and
multiplied by 2.
PC
disp
(sign-extended)
+
PC + disp × 2
×
2
Rev. 4.00 Sep. 13, 2007 Page 30 of 502
REJ09B0239-0400