SH7606 Datasheet, PDF (267/532 Pages) Renesas Technology Corp – 32-Bit RISC Microcomputer SuperH™ RISC engine Family / SH7606 Series

Section 12 Serial Communication Interface with FIFO (SCIF)
12.3.4 Transmit FIFO Data Register (SCFTDR)
SCFTDR is a 16-stage 8-bit FIFO register that stores data for serial transmission. When the SCIF
detects that the transmit shift register (SCTSR) is empty, it moves transmit data written in the
SCFTDR into SCTSR and starts serial transmission. Continuous serial transmission is performed
until there is no transmit data left in SCFTDR. SCFTDR can always be written to by the CPU.
When SCFTDR is full of transmit data (16 bytes), no more data can be written. If writing of new
data is attempted, the data is ignored.
SCFTDR is initialized to undefined value by a power-on reset.
Bit
7 to 0
Bit Name

Initial
value
R/W
Undefined W
Description
FIFO for transmits serial data
12.3.5 Serial Mode Register (SCSMR)
SCSMR is a 16-bit register that specifies the SCIF serial communication format and selects the
clock source for the baud rate generator.
The CPU can always read and write to SCSMR. SCSMR is initialized to H'0000 by a power-on
reset.
Bit
15 to 8
Bit Name

7
C/A
Initial
value
All 0
0
R/W Description
R Reserved
These bits are always read as 0. The write value should
always be 0.
R/W Communication Mode
Selects whether the SCIF operates in asynchronous or
synchronous mode.
0: Asynchronous mode
1: Synchronous mode
Rev. 4.00 Sep. 13, 2007 Page 241 of 502
REJ09B0239-0400