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SH7606 Datasheet, PDF (68/532 Pages) Renesas Technology Corp – 32-Bit RISC Microcomputer SuperH™ RISC engine Family / SH7606 Series | |||
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Section 2 CPU
Instruction
Operation
Code
Execution
Cycles T Bit
DMULU.L
Rm,Rn Unsigned operation of
0011nnnnmmmm0101 2 to 5*

Rn à Rm â MACH,
MACL 32 Ã 32 â 64 bits
DT Rn
Rn - 1 â Rn, if Rn = 0, 1 â 0100nnnn00010000 1
T, else 0 â T
Comparison
result
EXTS.B Rm,Rn
A byte in Rm is sign-
0110nnnnmmmm1110 1

extended â Rn
EXTS.W Rm,Rn
A word in Rm is sign-
0110nnnnmmmm1111 1

extended â Rn
EXTU.B Rm,Rn
A byte in Rm is zero-
0110nnnnmmmm1100 1

extended â Rn
EXTU.W Rm,Rn
A word in Rm is zero-
0110nnnnmmmm1101 1

extended â Rn
MAC.L @Rm+,@Rn+
Signed operation of (Rn) 0000nnnnmmmm1111 2 to 5*

à (Rm) + MAC â MAC,
32 Ã 32 + 64 â 64 bits
MAC.W @Rm+,@Rn+
Signed operation of (Rn) 0100nnnnmmmm1111 2 to 4*

à (Rm) + MAC â MAC,
16 Ã 16 + 64 â 64 bits
MUL.L Rm,Rn
Rn à Rm â MACL
32 Ã 32 â 32 bits
0000nnnnmmmm0111 2 to 5*

MULS.W Rm,Rn
Signed operation of Rn
0010nnnnmmmm1111 1 (3)*

à Rm â MAC
16 Ã 16 â 32 bits
MULU.W Rm,Rn
Unsigned operation of
0010nnnnmmmm1110 1 (3)*

Rn à Rm â MAC
16 Ã 16 â 32 bits
NEG Rm,Rn
0-Rm â Rn
0110nnnnmmmm1011 1

NEGC Rm,Rn
0-Rm-T â Rn,
Borrow â T
0110nnnnmmmm1010 1
Borrow
SUB Rm,Rn
Rn-Rm â Rn
0011nnnnmmmm1000 1

Rev. 4.00 Sep. 13, 2007 Page 42 of 502
REJ09B0239-0400
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