SH7606 Datasheet, PDF (255/532 Pages) Renesas Technology Corp – 32-Bit RISC Microcomputer SuperH™ RISC engine Family / SH7606 Series

Section 11 Compare Match Timer (CMT)
11.3 Operation
11.3.1 Interval Count Operation
When an internal clock is selected with bits CKS1 and CKS0 in CMCSR and the STR bit in
CMSTR is set to 1, CMCNT starts incrementing using the selected clock. When the values in
CMCNT and CMCOR match, CMCNT is cleared to H'0000 and the CMF flag in CMCSR is set
to 1. When the CMIE bit in CMCSR is set to 1, a compare match interrupt (CMI) is requested.
CMCNT then starts counting up again from H'0000.
Figure 11.2 shows the operation of the compare match counter.
CMCNT1 value
CMCOR1
Counter cleared by compare
match with CMCOR1
H'0000
Time
Figure 11.2 Counter Operation
11.3.2 CMCNT Count Timing
One of four internal clocks (Pφ/8, Pφ/32, Pφ/128, and Pφ/512) obtained by dividing the Pφ clock
can be selected with bits CKS1 and CKS0 in CMCSR. Figure 11.3 shows the timing.
Peripheral operating
clock (Pφ)
Count clock
CMCNT1
Nth
clock
(N + 1)th
clock
N
Figure 11.3 Count Timing
N+1
Rev. 4.00 Sep. 13, 2007 Page 229 of 502
REJ09B0239-0400