SH7606 Datasheet, PDF (126/532 Pages) Renesas Technology Corp – 32-Bit RISC Microcomputer SuperH™ RISC engine Family / SH7606 Series

Section 6 Interrupt Controller (INTC)
6.4.4 H-UDI Interrupt
User debugging interface (H-UDI) interrupt has a priority level of 15, and occurs when an H-UDI
interrupt instruction is serially input. H-UDI interrupt requests are detected by edge and are held
until accepted. H-UDI exception handling sets the interrupt mask level bits (I3-I0) in the status
register (SR) to level 15. For more details on the H-UDI interrupt, see section 17, User Debugging
Interface (H-UDI).
6.5 Interrupt Exception Handling Vector Table
Table 6.2 lists interrupt sources, their vector numbers, vector table address offsets, and interrupt
priorities.
Individual interrupt sources are allocated to different vector numbers and vector table address
offsets. Vector table addresses are calculated from the vector numbers and vector table address
offsets. For interrupt exception handling, the start address of the exception handling routine is
fetched from the vector table address in the vector table. For the details on calculation of vector
table addresses, see table 5.4, Calculating Exception Handling Vector Table Addresses in
section 5, Exception Handling.
IRQ interrupts and on-chip peripheral module interrupt priorities can be set freely between 0
and 15 for each pin or module by setting interrupt priority registers A to E (IPRA to IPRE).
However, when interrupt sources whose priority levels are allocated with the same IPR are
requested, the interrupt of the smaller vector number has priority. This priority cannot be changed.
Priority levels of IRQ interrupts and on-chip peripheral module interrupts are initialized to level 0
at a power-on reset. If the same priority level is allocated to two or more interrupt sources and
interrupts from those sources occur simultaneously, they are processed by the default priority
order shown in table 6.2.
Rev. 4.00 Sep. 13, 2007 Page 100 of 502
REJ09B0239-0400