SH7606 Datasheet, PDF (226/532 Pages) Renesas Technology Corp – 32-Bit RISC Microcomputer SuperH™ RISC engine Family / SH7606 Series

Section 8 Clock Pulse Generator (CPG)
Initial
Bit
Bit Name Value R/W
2
PFC2
0
R/W
1
PFC1
1
R/W
0
PFC0
1
R/W
Description
Peripheral Clock Frequency Division Ratio
Specify the division ratio of the peripheral clock
frequency with respect to the output frequency of PLL
circuit 1.
000: ×1
001: ×1/2
011: ×1/4
Other values: Setting prohibited
8.5 Changing Frequency
The internal clock frequency can be changed by changing the multiplication ratio of PLL circuit 1.
The peripheral clock frequency can be changed either by changing the multiplication ratio of PLL
circuit 1 or by changing the division ratio of divider 1. All of these are controlled by software
through the frequency control register. The methods are described below.
8.5.1 Changing Multiplication Ratio
The PLL lock time must be preserved when the multiplication ratio of PLL circuit 1 is changed.
The on-chip WDT counts for preserving the PLL lock time.
1. In the initial state, the multiplication ratio of PLL circuit 1 is 1.
2. Set a value that satisfies the given PLL lock time in the WDT and stop the WDT. The
following must be set.
 TME bit in WTCSR = 0: WDT stops
 Bits CKS2 to CKS0 in WTCSR: Division ratio of WDT count clock
 WTCNT: Initial counter value
3. Set the desired value in bits STC2 to STC0 while the MDCHG bit in STBCR is 0. The division
ratio can also be set in bits PFC2 to PFC0.
4. This LSI pauses internally and the WDT starts incrementing. The internal and peripheral
clocks both stop and only the WDT is supplied with the clock. The clock will continue to be
output on the CKIO pin.
5. Supply of the specified clock starts at a WDT count overflow, and this LSI starts operating
again. The WDT stops after it overflows.
Rev. 4.00 Sep. 13, 2007 Page 200 of 502
REJ09B0239-0400