SH7606 Datasheet, PDF (21/532 Pages) Renesas Technology Corp – 32-Bit RISC Microcomputer SuperH™ RISC engine Family / SH7606 Series

Figure 19.15 Byte Control SRAM Timing: SW = 1 Cycle, HW = 1 Cycle,
One Asynchronous External Wait Cycle, CSnWCR.BAS = 1
(WE-Controlled Write Cycle) ............................................................................... 457
Figure 19.16 Synchronous DRAM Single Read Bus Cycle
(Auto-Precharge, CAS Latency = 2, WTRCD = 0 Cycle, WTRP = 0 Cycle)...... 458
Figure 19.17 Synchronous DRAM Single Read Bus Cycle
(Auto-Precharge, CAS Latency = 2, WTRCD = 1 Cycle, WTRP = 1 Cycle)...... 459
Figure 19.18 Synchronous DRAM Burst Read Bus Cycle (Single Read × 4)
(Auto-Precharge, CAS Latency = 2, WTRCD = 0 Cycle, WTRP = 1 Cycle)....... 460
Figure 19.19 Synchronous DRAM Burst Read Bus Cycle (Single Read × 4)
(Auto-Precharge, CAS Latency = 2, WTRCD = 1 Cycle, WTRP = 0 Cycle)....... 461
Figure 19.20 Synchronous DRAM Single Write Bus Cycle
(Auto-Precharge, TRWL = 1 Cycle) ..................................................................... 462
Figure 19.21 Synchronous DRAM Single Write Bus Cycle
(Auto-Precharge, WTRCD = 2 Cycles, TRWL = 1 Cycle) .................................. 463
Figure 19.22 Synchronous DRAM Burst Write Bus Cycle (Single Write × 4)
(Auto-Precharge, WTRCD = 0 Cycle, TRWL = 1 Cycle) .................................... 464
Figure 19.23 Synchronous DRAM Burst Write Bus Cycle (Single Write × 4)
(Auto-Precharge, WTRCD = 1 Cycle, TRWL = 1 Cycle) .................................... 465
Figure 19.24 Synchronous DRAM Burst Read Bus Cycle (Single Read × 4) (Bank Active
Mode: ACT + READ Commands, CAS Latency = 2, WTRCD = 0 Cycle) ......... 466
Figure 19.25 Synchronous DRAM Burst Read Bus Cycle (Single Read × 4)
(Bank Active Mode: READ Command, Same Row Address,
CAS Latency = 2, WTRCD = 0 Cycle)................................................................ 467
Figure 19.26 Synchronous DRAM Burst Read Bus Cycle (Single Read × 4)
(Bank Active Mode: PRE + ACT + READ Commands,
Different Row Addresses, CAS Latency = 2, WTRCD = 0 Cycle) ..................... 468
Figure 19.27 Synchronous DRAM Burst Write Bus Cycle (Single Write × 4)
(Bank Active Mode: ACT + WRITE Commands,
WTRCD = 0 Cycle, TRWL = 0 Cycle)................................................................. 469
Figure 19.28 Synchronous DRAM Burst Write Bus Cycle (Single Write × 4)
(Bank Active Mode: WRITE Command, Same Row Address,
WTRCD = 0 Cycle, TRWL = 0 Cycle)................................................................. 470
Figure 19.29 Synchronous DRAM Burst Write Bus Cycle (Single Write × 4)
(Bank Active Mode: PRE + ACT + WRITE Commands,
Different Row Addresses, WTRCD = 0 Cycle, TRWL = 0 Cycle) ..................... 471
Figure 19.30 Synchronous DRAM Auto-Refreshing Timing
(WTRP = 1 Cycle, WTRC = 3 Cycles)................................................................. 472
Figure 19.31 Synchronous DRAM Self-Refreshing Timing (WTRP = 1 Cycle) ....................... 473
Figure 19.32 Synchronous DRAM Mode Register Write Timing (WTRP = 1 Cycle)............... 474
Rev. 4.00 Sep. 13, 2007 Page xxi of xxvi