SH7606 Datasheet, PDF (82/532 Pages) Renesas Technology Corp – 32-Bit RISC Microcomputer SuperH™ RISC engine Family / SH7606 Series

Section 3 Cache
show a match or the selected entry is not valid (V = 0), a cache miss occurs. Figure 3.2 shows a hit
on way 1.
Address
31
12 11
4 3 2 10
Entry selection
Longword (LW) selection
Ways 0 to 3
Ways 0 to 3
0 V U Tag address
1
LW0 LW1 LW2 LW3
255
CMP0 CMP1 CMP2 CMP3
Hit signal 1
CMP0: Comparison circuit 0
CMP1: Comparison circuit 1
CMP2: Comparison circuit 2
CMP3: Comparison circuit 3
Figure 3.2 Cache Search Scheme
3.3.2 Read Access
Read Hit: In a read access, instructions and data are transferred from the cache to the CPU. The
LRU bits are updated so that they point to the most recently hit way.
Rev. 4.00 Sep. 13, 2007 Page 56 of 502
REJ09B0239-0400