SH7606 Datasheet, PDF (217/532 Pages) Renesas Technology Corp – 32-Bit RISC Microcomputer SuperH™ RISC engine Family / SH7606 Series

Section 7 Bus State Controller (BSC)
If the CPU initiates read access for the cache, the cache is searched. If the cache stores data, the
CPU latches the data and completes the read access. If the cache does not store data, the CPU
performs four consecutive longword read cycles to perform cache fill operations via the internal
bus. If a cache miss occurs in byte or word operand access or at a branch to an odd word boundary
(4n + 2), the CPU performs four consecutive longword accesses to perform a cache fill operation
on the external interface. For a cache-through area, the CPU performs access according to the
actual access addresses. For an instruction fetch to an even word boundary (4n), the CPU performs
longword access. For an instruction fetch to an odd word boundary (4n + 2), the CPU performs
word access.
For a read cycle of a cache-through area or an on-chip peripheral module, the read cycle is first
accepted and then read cycle is initiated. The read data is sent to the CPU via the cache bus.
In a write cycle for the cache area, the write cycle operation differs according to the cache write
methods.
In write-back mode, the cache is first searched. If data is detected at the address corresponding to
the cache, the data is then re-written to the cache. In the actual memory, data will not be re-written
until data in the corresponding address is re-written. If data is not detected at the address
corresponding to the cache, the cache is updated. In this case, data to be updated is first saved to
the internal buffer, 16-byte data including the data corresponding to the address is then read, and
data in the corresponding access of the cache is finally updated. Following these operations, a
write-back cycle for the saved 16-byte data is executed.
In write-through mode, the cache is first searched. If data is detected at the address corresponding
to the cache, the data is re-written to the cache simultaneously with the actual write via the internal
bus. If data is not detected at the address corresponding to the cache, the cache is not updated but
an actual write is performed via the internal bus.
Since the BSC incorporates a 1-stage write buffer, the BSC can execute an access via the internal
bus before the previous external bus cycle is completed in a write cycle. If the on-chip module is
read or written after the external low-speed memory is written, the on-chip module can be
accessed before the completion of the external low-speed memory write cycle.
In read cycles, the CPU is placed in the wait cycle until read operation has been completed. To
continue the process after the data write to the device has been completed, perform a dummy read
to the same address to check for completion of the write before the next process to be executed.
The write buffer of the BSC functions in the same way for an access by a bus master other than
the CPU such as the DMAC or E-DMAC. Accordingly, to perform dual address DMA transfers,
the next read cycle is initiated before the previous write cycle is completed. Note, however, that if
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REJ09B0239-0400