SH7606 Datasheet, PDF (244/532 Pages) Renesas Technology Corp – 32-Bit RISC Microcomputer SuperH™ RISC engine Family / SH7606 Series

Section 10 Power-Down Modes
10.3.3 Standby Control Register 3 (STBCR3)
STBCR3 is an 8-bit readable/writable register that controls the operation of modules in power-
down mode.
Bit
7 to 5
4
3
2
1
0
Bit Name

Initial
Value
All 0
MSTP15 0

0
MSTP13 0
MSTP12 0
MSTP11 0
R/W Description
R Reserved
These bits are always read as 0. The write value should
always be 0.
R/W Module Stop Bit 15
When this bit is set to 1, the supply of the clock to the
CMT is halted.
0: CMT operates
1: Clock supply to CMT halted
R Reserved
This bit is always read as 0. The write value should
always be 0.
R/W Module Stop Bit 13
When this bit is set to 1, the supply of the clock to the
SCIF2 is halted.
0: SCIF2 operates
1: Clock supply to SCIF2 halted
R/W Module Stop Bit 12
When this bit is set to 1, the supply of the clock to the
SCIF1 is halted.
0: SCIF1 operates
1: Clock supply to SCIF1 halted
R/W Module Stop Bit 11
When this bit is set to 1, the supply of the clock to the
SCIF0 is halted.
0: SCIF0 operates
1: Clock supply to SCIF0 halted
Rev. 4.00 Sep. 13, 2007 Page 218 of 502
REJ09B0239-0400