SH7606 Datasheet, PDF (224/532 Pages) Renesas Technology Corp – 32-Bit RISC Microcomputer SuperH™ RISC engine Family / SH7606 Series

Section 8 Clock Pulse Generator (CPG)
4. The output frequency of PLL circuit 1 is the product of the frequency of the CKIO pin and the
multiplication ratio of PLL circuit 1. It is set by the frequency control register.
5. The bus clock frequency is always set to be equal to the frequency of the CKIO pin.
6. The clock mode, the FRQCR register value, and the frequency of the input clock should be
decided to satisfy the range of operating frequency specified in section 19, Electrical
Characteristics, with referring to table 8.3.
8.4 Register Descriptions
The CPG has the following registers.
For details on the addresses of these registers and the states of these registers in each processing
state, see section 18, List of Registers.
• Frequency control register (FRQCR)
8.4.1 Frequency Control Register (FRQCR)
FRQCR is a 16-bit readable/writable register that specifies whether a clock is output from the
CKIO pin in standby mode, the frequency multiplication ratio of PLL circuit 1, and the frequency
division ratio of the peripheral clock. Only word access can be used on FRQCR.
FRQCR is initialized by a power-on reset due to the external input signal. However, it is not
initialized by a power-on reset due to a WDT overflow.
Rev. 4.00 Sep. 13, 2007 Page 198 of 502
REJ09B0239-0400