SH7606 Datasheet, PDF (437/532 Pages) Renesas Technology Corp – 32-Bit RISC Microcomputer SuperH™ RISC engine Family / SH7606 Series

Section 17 User Debugging Interface (H-UDI)
17.4.2 Reset Configuration
Table 17.4 Reset Configuration
ASEMD*¹
RES
TRST
LSI State
High
Low
Low
Normal reset and H-UDI reset
High
Normal reset
High
Low
H-UDI reset only
High
Normal operation
Low
Low
Low
Reset hold*²
High
Normal reset
High
Low
H-UDI reset only
High
Normal operation
Notes: 1. Selects to normal mode or ASE mode.
ASEMD = high: normal mode
ASEMD = low: ASE mode
2. In ASE mode, the reset hold state is entered by driving the RES and TRST pins low for
the given time. In this state, the CPU does not start up, even if the RES pin is driven
high. After that, when the TRST pin is driven high, H-UDI operation is enabled, but the
CPU does not start up. The reset hold state is canceled by the following: another RES
assert (power-on reset) or TRST reassert.
17.4.3 TDO Output Timing
The timing of data output from the TDO differs according to the command type set in SDIR. The
timing changes at the TCK falling edge when JTAG commands (EXTEST, CLAMP, HIGHZ,
SAMPLE/PRELOAD, IDCODE, and BYPASS) are set. This is a timing of the JTAG standard.
When the H-UDI commands (H-UDI reset negate, H-UDI reset assert, and H-UDI interrupt) are
set, the TDO signal is output at the TCK rising edge earlier than the JTAG standard by a half
cycle.
Rev. 4.00 Sep. 13, 2007 Page 411 of 502
REJ09B0239-0400