SH7606 Datasheet, PDF (12/532 Pages) Renesas Technology Corp – 32-Bit RISC Microcomputer SuperH™ RISC engine Family / SH7606 Series

10.3.4 Standby Control Register 4 (STBCR4)................................................................. 219
10.4 Sleep Mode ........................................................................................................................ 220
10.4.1 Transition to Sleep Mode...................................................................................... 220
10.4.2 Canceling Sleep Mode .......................................................................................... 220
10.5 Software Standby Mode..................................................................................................... 220
10.5.1 Transition to Software Standby Mode .................................................................. 220
10.5.2 Canceling Software Standby Mode ...................................................................... 222
10.6 Module Standby Mode....................................................................................................... 223
10.6.1 Transition to Module Standby Mode .................................................................... 223
10.6.2 Canceling Module Standby Function.................................................................... 223
Section 11 Compare Match Timer (CMT) ........................................................ 225
11.1 Features.............................................................................................................................. 225
11.2 Register Descriptions......................................................................................................... 226
11.2.1 Compare Match Timer Start Register (CMSTR) .................................................. 226
11.2.2 Compare Match Timer Control/Status Register (CMCSR) .................................. 227
11.2.3 Compare Match Counter (CMCNT)..................................................................... 228
11.2.4 Compare Match Constant Register (CMCOR) ..................................................... 228
11.3 Operation ........................................................................................................................... 229
11.3.1 Interval Count Operation ...................................................................................... 229
11.3.2 CMCNT Count Timing......................................................................................... 229
11.4 Interrupts............................................................................................................................ 230
11.4.1 Interrupt Sources................................................................................................... 230
11.4.2 Timing of Setting Compare Match Flag ............................................................... 230
11.4.3 Timing of Clearing Compare Match Flag............................................................. 230
11.5 Usage Notes ....................................................................................................................... 231
11.5.1 Conflict between Write and Compare-Match Processes of CMCNT ................... 231
11.5.2 Conflict between Word-Write and Count-Up Processes of CMCNT ................... 231
11.5.3 Conflict between Byte-Write and Count-Up Processes of CMCNT..................... 232
11.5.4 Conflict between Write Processes to CMCNT with the Counting Stopped and
CMCOR................................................................................................................ 233
Section 12 Serial Communication Interface with FIFO (SCIF)........................ 235
12.1 Overview............................................................................................................................ 235
12.1.1 Features................................................................................................................. 235
12.2 Pin Configuration............................................................................................................... 238
12.3 Register Description .......................................................................................................... 239
12.3.1 Receive Shift Register (SCRSR) .......................................................................... 240
12.3.2 Receive FIFO Data Register (SCFRDR) .............................................................. 240
12.3.3 Transmit Shift Register (SCTSR) ......................................................................... 240
Rev. 4.00 Sep. 13, 2007 Page xii of xxvi