SH7606 Datasheet, PDF (304/532 Pages) Renesas Technology Corp – 32-Bit RISC Microcomputer SuperH™ RISC engine Family / SH7606 Series

Section 12 Serial Communication Interface with FIFO (SCIF)
Figure 12.3 shows a sample flowchart for initializing the SCIF.
Start of initialization
Clear TE and RE bits in SCSCR to 0
Set TFRST and RFRST bits
in SCFCR to 1
After reading BRK, DR, and ER flags
in SCFSR, and each flag in SCLSR,
write 0 to clear them
Set CKE1 and CKE0 bits
in SCSCR (leaving TE, RE, TIE,
[1]
and RIE bits cleared to 0)
Set data transfer format in SCSMR _[2]
Set value in SCBRR
[3]
Wait
No
1-bit interval elapsed?
Yes
Set RTRG1-0 and TTRG1-0 bits
in SCFCR, and clear TFRST
and RFRST bits to 0
Set TE and RE bits in SCSCR to 1, _[4]
and set TIE, RIE, and REIE bits
End of initialization
[1] Set the clock selection in SCSCR.
Be sure to clear bits TIE, RIE, TE,
and RE to 0.
[2] Set the data transfer format in
SCSMR.
[3] Write a value corresponding to the
bit rate into SCBRR. (Not
necessary if an external clock is
used.)
[4] Wait at least one bit interval, then
set the TE bit or RE bit in SCSCR
to 1. Also set the RIE, REIE, and
TIE bits.
Setting the TE bit enables the TxD
and RxD pins to be used.
When transmitting, the SCIF will go
to the mark state; when receiving,
it will go to the idle state, waiting for
a start bit.
Figure 12.3 Sample Flowchart for SCIF Initialization
Rev. 4.00 Sep. 13, 2007 Page 278 of 502
REJ09B0239-0400