SH7606 Datasheet, PDF (18/532 Pages) Renesas Technology Corp – 32-Bit RISC Microcomputer SuperH™ RISC engine Family / SH7606 Series

Figure 7.14 Basic Timing for Single Read (Auto Precharge)..................................................... 166
Figure 7.15 Basic Timing for Burst Write (Auto Precharge) ..................................................... 167
Figure 7.16 Basic Timing for Single Write (Auto-Precharge).................................................... 168
Figure 7.17 Burst Read Timing (No Auto Precharge) ................................................................ 170
Figure 7.18 Burst Read Timing (Bank Active, Same Row Address) ......................................... 171
Figure 7.19 Burst Read Timing (Bank Active, Different Row Addresses) ................................ 172
Figure 7.20 Single Write Timing (No Auto Precharge).............................................................. 173
Figure 7.21 Single Write Timing (Bank Active, Same Row Address)....................................... 174
Figure 7.22 Single Write Timing (Bank Active, Different Row Addresses).............................. 175
Figure 7.23 Auto-Refreshing Timing ......................................................................................... 176
Figure 7.24 Self-Refreshing Timing........................................................................................... 178
Figure 7.25 Write Timing for SDRAM Mode Register (Based on JEDEC)............................... 180
Figure 7.26 Basic Access Timing for Byte-Selection SRAM (BAS = 0)................................... 181
Figure 7.27 Basic Access Timing for Byte-Selection SRAM (BAS = 1)................................... 182
Figure 7.28 Wait Timing for Byte-Selection SRAM (BAS = 1) (Software Wait Only)............. 183
Figure 7.29 Example of Connection with 16-Bit Data-Width Byte-Selection SRAM ............... 184
Figure 7.30 Example of PCMCIA Interface Connection............................................................ 185
Figure 7.31 Basic Access Timing for PCMCIA Memory Card Interface................................... 186
Figure 7.32 Wait Timing for PCMCIA Memory Card Interface (TED[3:0] = B'0010,
TEH[3:0] = B'0001, Software Wait = 1, Hardware Wait = 1)................................. 186
Figure 7.33 Example of PCMCIA Space Assignment (CS5BWCR.SA[1:0] = B'10,
CS6BWCR.SA[1:0] = B'10) ................................................................................... 187
Figure 7.34 Basic Timing for PCMCIA I/O Card Interface ....................................................... 188
Figure 7.35 Wait Timing for PCMCIA I/O Card Interface (TED[3:0] = B'0010,
TEH[3:0] = B'0001, Software Wait = 1, Hardware Wait = 1)................................. 189
Figure 7.36 Timing for Dynamic Bus Sizing of PCMCIA I/O Card Interface
(TED[3:0] = B'0010, TEH[3:0] = B'0001, Software Waits = 3) ............................. 189
Section 8 Clock Pulse Generator (CPG)
Figure 8.1 Block Diagram of CPG ............................................................................................. 194
Figure 8.2 Points for Attention When Using Crystal Resonator................................................. 203
Section 9 Watchdog Timer (WDT)
Figure 9.1 Block Diagram of WDT ............................................................................................ 206
Figure 9.2 Writing to WTCNT and WTCSR.............................................................................. 210
Section 10 Power-Down Modes
Figure 10.1 Canceling Standby Mode with STBY Bit in STBCR.............................................. 222
Section 11 Compare Match Timer (CMT)
Figure 11.1 Block Diagram of Compare Match Timer............................................................... 225
Figure 11.2 Counter Operation ................................................................................................... 229
Rev. 4.00 Sep. 13, 2007 Page xviii of xxvi