SH7606 Datasheet, PDF (183/532 Pages) Renesas Technology Corp – 32-Bit RISC Microcomputer SuperH™ RISC engine Family / SH7606 Series

Section 7 Bus State Controller (BSC)
Table 7.10 Relationship between Register Settings and Address Multiplex Output (1)
Conditions: One 16-Mbit product (512 kwords x 16 bits x 2 banks, 8-bit column product) is
connected with A3BSZ[1:0] = 10 (16-bit data bus width), A3ROW[1:0] = 00 (11-bit
row address), and A3COL[1:0] = 00 (8-bit column address).
Output Row
Pins of this LSI Address
Output Column
Address
Pins of SDRAM Function
A17
A25
A17
Unused
A16
A24
A16
A15
A23
A15
A14
A22
A14
A13
A21
A21
A12
A20*²
A20*²
A11 (BA0)
Specifies bank
A11
A19
L/H*¹
A10/AP
Specifies
address/precharge
A10
A18
A10
A9
Address
A9
A17
A9
A8
A8
A16
A8
A7
A7
A15
A7
A6
A6
A14
A6
A5
A5
A13
A5
A4
A4
A12
A4
A3
A3
A11
A3
A2
A2
A10
A2
A1
A1
A9
A1
A0
A0
A8
A0
Unused
Notes: 1. L/H is a bit used in the command specification; it is fixed low or high according to the
access mode.
2. Bank address specification
Rev. 4.00 Sep. 13, 2007 Page 157 of 502
REJ09B0239-0400