SH7606 Datasheet, PDF (162/532 Pages) Renesas Technology Corp – 32-Bit RISC Microcomputer SuperH™ RISC engine Family / SH7606 Series

Section 7 Bus State Controller (BSC)
Initial
Bit
Bit Name Value R/W Description
14
TED3
0
R/W Delay from Address to RD or WE Assert
13
TED2
0
R/W Specify the delay time from address output to RD or WE
12
TED1
0
R/W ^{assertion in PCMCIA interface.}
11
TED0
0
R/W ^{0000: 0.5 cycles}
0001: 1.5 cycles
0010: 2.5 cycles
0011: 3.5 cycles
0100: 4.5 cycles
0101: 5.5 cycles
0110: 6.5 cycles
0111: 7.5 cycles
1000: Reserved (setting prohibited)
1001: Reserved (setting prohibited)
1010: Reserved (setting prohibited)
1011: Reserved (setting prohibited)
1100: Reserved (setting prohibited)
1101: Reserved (setting prohibited)
1110: Reserved (setting prohibited)
1111: Reserved (setting prohibited)
10
PCW3
1
R/W Number of Access Wait Cycles
9
PCW2
0
R/W Specify the number of wait cycles to be inserted.
8
PCW1
1
R/W 0000: 3 cycles
7
PCW0
0
R/W ^{0001: 6 cycles}
0010: 9 cycles
0011: 12 cycles
0100: 15 cycles
0101: 18 cycles
0110: 22 cycles
0111: 26 cycles
1000: 30 cycles
1001: 33 cycles
1010: 36 cycles
1011: 38 cycles
1100: 52 cycles
1101: 60 cycles
1110: 64 cycles
1111: 80 cycles
Rev. 4.00 Sep. 13, 2007 Page 136 of 502
REJ09B0239-0400