SH7606 Datasheet, PDF (413/532 Pages) Renesas Technology Corp – 32-Bit RISC Microcomputer SuperH™ RISC engine Family / SH7606 Series

Section 16 User Break Controller (UBC)
Initial
Bit
Bit Name Value R/W Description
6
PCBB
0
R/W PC Break Select B
Selects the break timing of the instruction fetch cycle for
channel B as before or after instruction execution.
0: PC break of channel B is set before instruction
execution
1: PC break of channel B is set after instruction
execution
5, 4
—
All 0 R
Reserved
These bits are always read as 0. The write value should
always be 0.
3
SEQ
0
R/W Sequence Condition Select
Selects two conditions of channels A and B as
independent or sequential conditions.
0: Channels A and B are compared under independent
conditions
1: Channels A and B are compared under sequential
conditions (channel A, then channel B)
2, 1
—
All 0 R
Reserved
These bits are always read as 0. The write value should
always be 0.
0
ETBE
0
R/W Number of Execution Times Break Enable
Enables the execution-times break condition only on
channel B. If this bit is 1 (break enable), a user break is
issued when the number of break conditions matches
with the number of execution times that is specified by
BETR.
0: The execution-times break condition is disabled on
channel B
1: The execution-times break condition is enabled on
channel B
16.2.10 Execution Times Break Register (BETR)
BETR is a 16-bit readable/writable register. When the execution-times break condition of channel
B is enabled, this register specifies the number of execution times to make the break. The
maximum number is 2¹² – 1 times. Every time the break condition is satisfied, BETR is
Rev. 4.00 Sep. 13, 2007 Page 387 of 502
REJ09B0239-0400