SH7606 Datasheet, PDF (353/532 Pages) Renesas Technology Corp – 32-Bit RISC Microcomputer SuperH™ RISC engine Family / SH7606 Series

Section 13 Host Interface (HIF)
External Device
This LSI
No. CPU
DMAC
HIF
CPU
12
Write to end → HIF bank → HIFRAM bank switching
address of bank interrupt
by HIF bank interrupt
0 in HIFRAM
occurs
handler (external device
completes and
accesses bank 1 and on-
operation halts
chip CPU accesses
bank 0)
13
Re-activate
← Assert
← Set DTRG bit to 1
DMAC
HIFDREQ
Hereafter No. 11 to 13 are repeated. When a register other than HIFDATA is accessed (except
that HIFGSR read with HIFRS = low), HIFRAM consecutive write is interrupted, and No. 3 to 6
need to be done again.
Table 13.5 Consecutive Read Procedure from HIFRAM by External DMAC
External Device
No. CPU
DMAC
HIF
1
HIF initial setting
2
DMAC initial setting
3
Set HIFADR to
HIFRAM start
address
4
Set HIFRAM
consecutive read with
address increment in
HIFMCR
5
Select HIFDATA
6
7
8
Activate DMAC ← Assert
HIFDREQ
This LSI
CPU
HIF initial setting
Write data to bank 1 in
HIFRAM
After writing data to end
address of bank 1 in
HIFRAM, perform
HIFRAM bank switching
(external device
accesses bank 1 and on-
chip CPU accesses
bank 0)
← Set DTRG bit to 1
Rev. 4.00 Sep. 13, 2007 Page 327 of 502
REJ09B0239-0400