MC68HC912BD32 Datasheet, PDF (99/292 Pages) Freescale Semiconductor, Inc – Advance Information

Freescale Semiconductor, Inc.
Resets and Interrupts
Effects of Reset
Clock and
Watchdog Control
Logic
The COP watchdog system is enabled, with the CR [2:0] bits set for the
shortest duration time-out. The clock monitor is disabled. The RTIF flag
is cleared and automatic hardware interrupts are masked. The rate
control bits are cleared, and must be initialized before the RTI system is
used. The DLY control bit is set to specify an oscillator start-up delay
upon recovery from STOP mode.
Interrupts
PSEL is initialized in the HPRIO register with the value $F2, causing the
external IRQ pin to have the highest I-bit interrupt priority. The IRQ pin
is configured for level-sensitive operation (for wired-OR systems).
However, the interrupt mask bits in the CPU12 CCR are set to mask X
and I related interrupt requests.
Parallel I/O
If the MCU comes out of reset in an expanded mode, port A and port B
are used for the multiplexed address/data bus and port E pins are
normally used to control the external bus (operation of port E pins can
be affected by the PEAR register). If the MCU comes out of reset in a
single-chip mode, all ports are configured as general-purpose
high-impedance inputs. Port S, port T, port DLC, port P, and port AD are
all configured as general-purpose inputs.
Central Processing
Unit
After reset, the CPU fetches a vector from the appropriate address, then
begins executing instructions. The stack pointer and other CPU registers
are indeterminate immediately after reset. The CCR X and I interrupt
mask bits are set to mask any interrupt requests. The S bit is also set to
inhibit the STOP instruction.
Memory
After reset, the internal register block is located at $0000–$01FF, the
register-following space is at $0200–$03FF, and RAM is at
$0800–$0BFF. EEPROM is located at $0D00–$0FFF. Flash EEPROM
is located at $8000–$FFFF in single-chip modes and at $0000–$7FFF
(but disabled) in expanded modes.
Other Resources
7-resets
The timer, serial communications interface (SCI), serial peripheral
interface (SPI), Byteflight™, pulse-width modulator (PWM), and
analog-to-digital converter (ATD) are off after reset.
Resets and Interrupts
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MC68HC912BD32 Rev 1.0